1. Field of the Invention
The present invention relates to a semiconductor memory device having a split transfer function, provided with a random access port and a serial access port, and, in particular, to a semiconductor memory device used for a high speed graphic memory.
2. Description of the Prior Art
It is well known that a dual-port semiconductor memory device having both a random access memory (RAM) and a serial access memory (SAM) is commonly used as a memory for graphics.
This type of a dual-port memory has, for example, a configuration such as that illustrated in FIG. 1.
FIG.1 is the configuration diagram of the dual-port semiconductor memory. In FIG. 1, data in the dynamic random access memory cells (512.times.512.times.4 random access memory cell array) are transferred to registers in an upper SAM or registers in a lower SAM through transfer gate. The data in the registers in the upper SAM and the lower SAM are selected by serial selectors 87 and transferred to an external device (not shown). An address to select one of the register in the upper SAM and the lower SAM by the serial selectors 87 is transferred from a serial address counter 80.
In normal usage, data stored in memory cells in a row in the RAM are transferred to registers in a SAM, and the data in the registers in the SAM are transferred serially to a display device (not shown) through a serial output buffer to display the data on a screen in the display device. A split transfer mode has been used in order to transmit the data in the memory cells in the row in the RAM to the registers in the SAM and to transfer the data to an external device through the serial output buffer, with good efficiency.
A split transfer under the split transfer mode is a mode in which memory cells in a row are divided into two parts and then data in the memory cells is transferred to the registers in two parts in the SAM alternately. In a normal readout transmission, synchronization of the timing of the data transfer from the RAM to the SAM and the timing of the input of a serial clock SC is very strict so that the data output from the SAM occurs without interruption because the next transfer data must be transferred to the registers in the SAM from the memory cells in a next row while an address pointer indicating a readout position in the registers in the SAM returns to a start address position in the registers of the SAM.
However, in the split transfer mode, by dividing the SAM into two parts (upper SAM and lower SAM), for example, there are no strict timing requirements and the output from the registers in the SAM can take place without interruption because data in the memory cells in the RAM are transferred to the upper SAM while data in the registers of the lower SAM are transferred to an external device (not shown).
The data readout from the registers of the SAM under the split transfer mode is initiated at the register addressed by a TOP Address Point ("TAP") which has been set in this split transfer cycle (SRT cycle) and the data readout is completed at the register indicated by a boundary address which has been previously set.
The registers in the SAM are divided into 2.sup.n parts (where n=1, 2, 3, . . . ) by using boundary addresses so that the data read out from the registers in the SAM are efficiently displayed on the screen. In the case where the data readout from the registers in the SAM are in a continuous split transfer mode, a pointer indicating an address of the register in the SAM jumps to a register in the SAM as a next data readout position indicated by a next TAP address for a next split transfer after a pointer indicating the register in the SAM as a readout position reaches a boundary address of the current split transfer.
A control signal QSF, the SAM counter address, the boundary address, and the TAP address are used for pointing the address of a register in the SAM. The control signal QSF indicates one of the upper SAM and the lower SAM. For example, if the control signal QSF is at the high level, the upper SAM is selected, if at the low level, the lower SAM is selected.
The control method for a SAM counter address and the control signal QSF will now be described with reference to FIGS. 1 to 4.
FIG. 2 is a detailed configuration diagram mainly showing the serial address counter 80 in the dual-port semiconductor memory device shown in FIG. 1.
FIG. 3 is a timing chart to explain a relationship among main internal signals which are used to control an operation of a SAM counter address (SAi) 72 and a control signal QSF under a continuous split transfer mode.
FIG. 4 is a configuration diagram of a circuit used for controlling a conventional split transfer operation.
In order to simplify an explanation, the memory cells in the RAM which are the core section of the dual port semiconductor memory device shown in FIG. 1 are divided into two. Registers 512 addressed by the SAM addresses in the SAM including an upper SAM and a lower SAM have 512 bits (0 to 511). Boundary addresses are 127, 255, 383, and 511. In addition, a control signal SC(n) indicates the n-th register in the SAM, and a SRT(m) indicates a split transfer mode or cycle having a tap address of m. In the case shown in FIG. 3, the first split transfer SRT1 cycle has two tap addresses, 255 and 511 and the boundary addresses of 127, 255, 383, and 511 are set in a boundary address register 86 shown in FIGS. 1 and 2. The second split transfer mode has the TAP address of 100.
As shown in FIG. 1, a TAP address is transferred to a first internal address register 81 in the serial address counter 80 from a column address buffer (register) 71 of 9 bits through first transfer gate 810 while a column address strobe signal /CAS is at the low level.
Boundary addresses are transferred to a boundary address register 86 from a row address buffer (9 bits) 60 when a row address strobe signal /RAS is changed to the low level.
In FIG. 2, a TAP address for indicating the data in a register in a row of the RAM is latched into a first internal address register 81 in the serial address counter 80. When the TAP address latched into the first internal address register 81 is transferred to a second internal address register 82 when a SAM counter address (SAi) in the SAM counter address register 72 is agreed with a boundary address stored in the boundary address register 86 by a first comparator 84 in the QSF circuit 800. When agreed, the first comparator 84 generates an agreement signal (which are control signals TAPLC2 described later) and transmits the agreement signal TAPLC2 to the second transfer gate 820 located between the first internal address register 81 and the second internal address register 82. By receiving the agreement signal TAPLC2 from the first comparator 84, the second transfer gate 820 transfers the TAP address stored in the first internal address register 81 to the second internal address register 82.
The column address or the TAP address stored in the second internal address register 82 is transferred to the third internal address register in the third internal address register 83 when receiving a control signal FSCT. This control signal FSCT is generated by the first comparator 84 when a first serial clock SC is received after the SAM counter address SAi is agreed with the boundary address BDAi.
Then, the TAP address stored in the third internal address register in the third internal address register 83 is transferred to the SAM counter address register 72.
A control signal QSF is generated by a QSF generator in a second comparator 85 in the QSF circuit 800 as a result of comparing the SAM counter address SAi in the SAM counter address register 72, the boundary address stored in the boundary address register 86, and an address stored in the first internal address register 81. The control signal QSF switches a SAM switch in order to select one of the upper SAM and the lower SAM to transfer data in the registers in the upper SAM or the lower SAM to an external device.
Data in the registers in the upper SAM are transferred to the external device while the control signal QSF is at the high level and data in the registers in the lower SAM are transferred to the external device when the control signal QSF is at the low level.
In controlling the SAM counter address in the SAM counter address register 72, with a SAM counter address (SAi) is incremented by "1" such as SAi=(SAi +1) according to receive the serial clock SC under the normal operation mode, not under the split transfer mode.
In the normal operation mode, the SAM counter address is returned to zero "0" when the SAM counter address is reached to "511" (or to the 511-th registers).
In addition, in the split transfer mode, the value of the SAM counter address (SAi) is changed by receiving a next TAP address which has been set when the SAM counter address (SAi) points to the register in the SAM addressed by the boundary address.
In the timing chart as shown in FIG. 3, when a following serial clock SC (383) is received at the timing T1 by the first comparator 84 (which is also transferred to the SAM counter address register 72 at the same time) in the split transfer SRT1 cycle (TAP addresses are 255 and 511), the first comparator 84 compares a boundary address (BDAj=383) stored in the boundary address register 86 with the SAM counter address (SAi=383) in the SAM counter address register 72, then shows agreement of them, the first comparator 84 generates a control signal STPA of the high level at the timing T2 shown in FIG. 3 and FIG. 4A. The control signal STPA changes to the high level when the serial clock SC is agreed with the boundary address compared by the first comparator 84.
A control signal SPLTC indicates the split transfer mode with the high level. A control pulse signal TAPLC2 of the low level is generated when the control signal STPA changes to the high level and the control signal SPLTC is at the high level at the timing T2 (shown in FIG. 3 and FIG. 4A). When the pulse signal TAPLC2 of the low level is generated at the timing T2, a TAP address (255) stored in the first internal address register 81 is transferred to the second internal address register 82.
FIG. 4A shows a configuration diagram of the first comparator for the control signals STPA and TAPLC2. Thus, the control pulse signal TAPLC2 is generated when the serial clock SC is agreed with the boundary address.
Then, a following serial clock SC is received by the SAM counter address (SAi) register 72 and the first comparator 84. The first comparator 84 generates and transmits the first serial clock SC acknowledge control signal FSCT of the high level to the third transfer register 830. By this, the TAP address (255) stored in the second internal address register 82 is transferred to the third internal address register 83, then, the TAP address is set to the SAM counter address register 72 as a new SAM counter address.
The value of the control signal QSF is changed by using the control signals NLM1SC and the ATAP signals. The control signal ATAP is changed to the high level when the value of the SAM counter address register 72 is agreed with the boundary address stored in the boundary address register 86.
The control signal NLM1SC is used for a WRAP AROUND mode which is the normal operation mode, not under the split transfer mode. The control signal NLM1SC is changed from the low level to the high level when the SAM counter address (SAi) 72 is agreed with the boundary address-1. By using the control signal NLM1SC, the control signal QSF is changed within two cycles.
It requires more than two cycles to change the control signal QSF after the first comparator 84 decides that the serial clock SC is agreed with the boundary address stored in the boundary address register 86.
The control signal NLM1SC is changed to the high level when the serial clock SC is equal to the cycle of the boundary address-1, for example at the timing T4 shown in FIG. 3. In this case, data in the memory cells in the upper RAM or the lower RAM are latched into the registers in one of the upper SAM and the lower SAM indicated by the control signal QSF. The data stored in the registers in the SAM are transferred to an external device (not shown) from the SC cycle in which the serial clock SC is agreed with the boundary address.
On the contrary when a first serial clock 1st-SC after the boundary address is agreed with the address stored in the SAM counter address register 72 is received at the first comparator 84 after the SRT2 cycle, this 1st-SC is the first SC for the first split transfer SRT1 cycle and this serial clock SC (255) is equal to the boundary address for the next split transmission SRT2 cycle. Accordingly, the value of the control signal QSF must be changed and a next TAP address (100) for the next split transfer SRT2 cycle must be set into the third internal address register 83. In this case, there is no serial clock SC which is a boundary address-1. In other words, the control signal NLM1SC has no high level pulse after the SRT2 (100) cycle. This is a problem. In order to avoid this problem, a control signal ATAP is used in the conventional dual-port semiconductor memory device.
The control signal ATAP is generated by the circuit shown in FIG. 4B.
This control signal ATAP changes to the high level and latched by a latch circuit 400 shown in FIG. 4B only when the TAP address is agreed with the boundary address, for example at the timing T2 shown in FIG. 3. This control signal ATAP is used like the control signal NLM1SC under the wrap around operation mode which has already been described in brief. In other words, the level of the control signal QSF is changed when a following serial clock SC is received while the control signal ATAP is at the high level.
FIG. 4B shows a configuration diagram of the generation circuit for the control signals ATAP, SQXF, and QSF.
We use following three modes or cycles (1) to (3) for readout data from the conventional dual-port semiconductor memory device.
(1) CBRS mode is a /CAS before /RAS refresh stop register set mode. A boundary address can be changed in the CBRS mode.
(2) SRT mode is a split transfer mode (SRT mode) which has been described above.
(3) CBR mode is a /CAS before /RAS refresh option reset mode (CBR mode). In the CBR mode, registers in a SAM are divided into two SAM, each of which is a same memory size and a boundary address is reset for the two SAM. For example, a SAM address is 0 to 511, the address of the registers in the first SAM is 0 to 255, and the address of the registers in the second SAM is 256 to 511. In the CBR mode, the addresses 255 and 511 are set as the boundary addresses.
With this type of a conventional memory, irregularities are produced in one part of the composite modes CBRS (/CAS before /RAS refresh stop register set), SRT (split transfer), and CBR (/CAS before /RAS refresh option reset).
Three of these irregular modes are given below and these problem areas are explained.
First, FIG. 5 is a timing chart for a conventional first SAM composite mode (example 1).
In FIG. 5, boundary addresses can be changed only in the CBRS and CBR cycles. In the case of the CBRS cycle a new boundary address is effective following to the split transfer SRT cycle after the CBRS cycle. For this reason, the internal boundary address is changed with a new boundary address after a falling edge (at timing T50) of the row address strobe /RAS for the SRT2 cycle in the example 1 shown in FIG. 5.
As shown in FIG. 5, the boundary addresses are 255, 511 (two division) in the SRT1 cycle. Following the CBRS cycle, the boundary addresses are changed to new boundary addresses, 127, 255, 383, and 511 (four division) at the timing T50 after the SRT2 cycle. Thus, the boundary addresses are changed only after the CBRS cycle and the CBR cycle.
After the boundary addresses are changed in the SRT2 cycle at the timing T50, a comparison operation is made of the SAM counter address (127) stored in the SAM counter address register 72 and the new boundary addresses (127, 255, 383, 5111) stored in the boundary address register 86 by the first comparator 84.
The serial clock SC(127) is received at the timing T51 and set into the SAM counter address register 72. This SC (127 designated by the character reference "*b") is equal to one of the new boundary addresses(127, 255, 383, and 511) of the four division by comparing at the timing T50 before receiving the next serial clock SC(383) at the timing T52 designated by the character reference "*c". Thus, the control signal STPA changes to the high level at the timing T50 shown in FIG. 5.
At the timing T50, the conventional dual-port semiconductor memory is in the split transfer mode because the control signal SPLTC is at the high level, so that the pulse of the low level of the control signal TAPLC2 is generated (designated by "*h" shown in FIG. 5), because the serial clock (127) is equal to one of the boundary addresses (127, 255, 383, and 511 in the four division). Then, the TAP address (383) of the SRT1 cycle is transferred into the SAM counter address register 72 at the timing T52. An erroneous operation is occurred for the SAM counter address register 72.
On the other hand, in the WRAP AROUND mode which is not a split transfer mode, the SAM counter address (SAi) in the SAM counter address register 72 must be "128" by receiving the first serial clock SC immediately after the SRT2 cycle at which TAP addresses 127 and 383 are set into the SAM counter address register 72.
However, the TAP address (383) set in the SRT1 cycle is set into the SAM counter address register 72 because the SRT2 cycle is occurred after the CBRS cycle (the four division). An erroneous operation is occurred for the SAM counter address register 72.
The combination mode (CBRS cycle and SRT2 cycle) represents the conditions under which this type of erroneous operation is produced because the number of boundary addresses is increased. In other words, the erroneous operation will be happened in the case where the boundary addresses are not equal to the SAM counter address in the SAM counter address register 72 before the boundary addresses are changed at the timing T50 and one of the boundary addresses is equal to the SAM counter address in the SAM counter address register 72 after the boundary addresses are changed at the timing T50.
This type of error or restriction is produced because the control signal STPA is changed to the high level by the result of the comparing operation between the SAM counter address and the new boundary address at the timing T50 after the boundary address change in the SRT2 cycle after the CBRS cycle.
Next, FIG. 6 is a timing chart for a second conventional SAM composite mode (Example 2).
In the example 2 shown in FIG. 6, boundary addresses are 127, 255, 383, and 511 (in four division) during the SRT1 cycle. At the timing T60 after the SRT1 cycle (shown as "*d" in FIG. 6), the control signal QSF is changed from the low level to the high level by receiving the serial clock SC(127) because the serial clock SC (127) is equal to the boundary address (127).
Subsequently, a dummy SRT (DSRT) cycle in which the serial clock SC is not received, a CBRS cycle (two division), and a SRT2 cycle are executed.
At the timing T65, the new TAP address (383) is set into the SAM counter address register 72 by the low level pulse of the control signal TAPLC2. This TAP address (383) is equal to the boundary address at the timing T61, so that the control signal ATAP is changed to the high level and latched by the latch circuit 400, as shown in FIG. 4B.
In this case, the control signal ATPA is changed to the high level from the low level at the timing T61 in the Dummy SRT cycle (DSRT cycle) before changing to new boundary addresses (255/511) of the two division by the CBRS cycle.
However, by the execution of the CBRS cycle prior to the SRT2(127/383) cycle the serial clock SC(383) (or the TAP address(383)) is no longer the boundary address after the boundary address are changed to the new boundary addresses (255 and 511) at the timing T63, therefore the control signal ATAP must be changed to the low level at the timing T63. However, the signal ATAP is latched by the latch circuit 400 shown in FIG. 4B and this latch is released only by entering a following serial clock SC (383) at the timing T62. As shown in FIG. 4B, the control signal TMPC is at the high level while a next serial clock SC is received after the completion of the split transmission mode.
Accordingly, even if the boundary address is changed at the timing T63 in this case, the signal ATAP of the high level is latched from the timing T61 to the timing T62 because a next serial clock SC is not received before the timing T62. For this reason, the control signal QSF produces an erroneous operation at the timing T64 immediately after the receiving of the first serial clock SC (383) designated by the character reference "*e" at the timing T62. The level of the control signal QSF is changed to the low level at the timing T64. This is a problem. The control signal QSF must not be changed to the low level at the timing T64.
As the conditions under which this type of erroneous operation is produced, the case occurs wherein the modes DSRT+CBRS+SRT are executed in the time interval following the change in the control signal QSF to the high level at the timing T10 until the first serial clock SC (383) at the timing T60, the number of the boundary addresses is changed into a rough division (from the four division (127, 255, 383, and 511) to the two division (255, 511) by the CBRS cycle and it is considered that the TAP address is equal to the boundary address prior to the CBRS cycle, and the TAP address is not equal to the boundary address after the CBRS cycle.
This type of restriction is produced because a pulse is generated in a control signal TAPLC1 by entering the DSRT cycle and it is not possible to hold the TAP address for the SRT1 cycle because the TAP address for the dummy SRT cycle is superscribed in the SAM counter address register 72 in which the data which is to be compared with the boundary is stored. In addition to this a boundary address change is produced, and even though there is no necessity for the signal QSF to be changed, there is no function for releasing the latching of the control signal ATAP in this conventional dual-port semiconductor memory configuration shown in FIGS. 1, 2, 4A, and 4B.
Finally, FIG. 7 is a timing chart for a third conventional SAM composite mode (Example 3).
In the Example 3 shown in FIG. 7, the boundary addresses for the SRT1 cycle are 127, 255, 383, and 511 which are stored in the boundary address register 86. The level of the control signal QSF is changed to the high level from the low level at the timing T70 after the serial clock SC(127) shown as "*f" in FIG. 7 is received, because the SAM counter address (127) in the SAM counter address register 72 is equal to the boundary address (127). Subsequently, the SRT2 cycle and the CBR cycle follow. In the case of the CBR cycle, the boundary addresses (127, 255, 383, and 511 for the four division) are changed to new boundary addresses (255 and 511 for the two division) at the timing T71 immediately following the CBR cycle.
In the conventional SAM composite mode (Example 3), like the second composite mode (Example 2) shown in FIG. 6, a new TAP address is set into the SAM counter address register 72 because the low pulse of the control signal TAPLC2 is generated at the timing T75. After the level of the control signal QSF is changed to the high level at the timing T70 and before the change of the boundary addresses at the timing T71, the TAP address (383) in the SAM counter address register 72 is equal to the boundary address (383). By this, the level of the control signal ATAP is changed to the high level at the timing T72.
However, the serial clock SC(383) designated by the reference character "*g" is not equal to the boundary address after the boundary addresses are changed at the timing T71 in the CBR cycle, therefore the control signal ATAP must be changed to the low level. However, this control signal ATAP is latched by the latch circuit 400 shown in FIG. 4B and this latch can be released by using the control signal TMPC generated only by receiving a next serial clock SC.
Accordingly, even if the boundary address is changed in the CBR cycle, the next serial clock (383) designated by the reference "*g" is not received before the timing T73, so that the erroneous of the control signal QSF is occurred at the timing T74 at which the first serial clock SC (383) is received. At the timing T74, the level of the control signal QSF must not be changed to the low level.
As the conditions under which this type of erroneous operation is occurred, the case occurs wherein the SRT cycle and CBR cycle are executed after the level of the control signal QSF is changed to the high level at the timing T70 and before the first serial clock CK (383) is received at the timing T73. It is recognized that the TAP address (383) is equal to the boundary address (383) prior to the execution of the CBR cycle or before the timing T71. In addition, the TAP address (383) is not equal to the new boundary addresses (255/511) after the timing T71 in the CBR cycle.
As in the case of the Example 2 shown in FIG. 6, this type of restriction occurs because a pulse is generated in the control signal TAPLC1 at the timing T72 by the SRT2 cycle and it is not possible to store the TAP address for the SRT1 cycle because the TAP address for the SRT2 cycle is superscribed in the SAM counter address register 72 in which the data to be compared with the boundary addresses is stored. In addition to this a boundary address change is occurred, and even though there is no necessity for the control signal QSF to be changed at the timing T74, there is no function for releasing the latching of the control signal ATAP in the dual-port memory having this conventional configuration.
As can be understood from the foregoing explanation for the conventional dual-port memory, in a conventional dual-port semiconductor memory device provided with a split transfer function, erroneous operation is produced from the selecting of the upper SAM and the lower SAM in the SAM in a composite mode made up of the above-described split transfer mode, CBRS mode, and CBR mode.